Wireless base stations in cellular networks need to be mutually synchronized for seamless transition (handover) of calls when a wireless phone user moves between wireless cell boundaries and also to support some additional services (for example, location services).
In general, cells in a wireless network can be synchronized in any, and all of, frequency, phase and time-of-day. Frequency synchronization assumes that local clocks in each cell have the same frequency. This can be achieved if all cells are frequency synchronized to some master clock via T1/E1/Synchronous Ethernet links. Traditional Ethernet is an asynchronous packet network protocol, which does not assume that the nodes are synchronized to a common source. In synchronous Ethernet clock signals are transferred over the Ethernet physical layer so that all nodes are synchronized to a common source.
Phase synchronization requires that clock transitions at each cell occur at the same time. If cells are synchronized in phase they have to be synchronized in frequency as well, otherwise the clock phases of corresponding cells will drift relative to each other. Clocks can be synchronized in phase and frequency to each other without being synchronized to standard time (Universal Coordinated Time).
Time-of-day synchronization assumes that each node knows the exact time of the day relative to universal coordinated time at any instant and the time-of-day difference between any two nodes is very small, in practice less than 1.5 μs.
Synchronization in synchronous Ethernet is achieved in much the same way as in SONET/SDH networks where all nodes are synchronized only in frequency (not time-of-day) to a Primary Reference Clock (PRC). The PRC is a free running atomic clock or clock traceable to an atomic clock with a frequency accuracy better than 10−11. There is however no provision for time-of-day synchronization in synchronous Ethernet. Although the PRC driving synchronous Ethernet network is very accurate, the synchronous Ethernet standard, as defined by ITU-T Rec. G8261, 8262 and 8264, does not require the PRC to be synchronized to Coordinated Universal Time (UTC). The frequency generated by the synchronous Ethernet PRC can be up to 10−11 off the frequency of the UTC master clock, which translates to error that accumulates at the rate of 36 ns/hour. Consequently, the PRC cannot be used to generate time-of-day information.
Time-of-day synchronization can be achieved by synchronizing local clocks via GPS signals or using the IEEE 1588 protocol. Synchronization in accordance with IEEE 1588 is achieved by transmitting time-stamped timing packets over the Ethernet network from a master clock synchronized to UTC. Due to the stochastic nature of packet queuing in network nodes, propagation delay varies from packet to packet. In general, packet propagation delay increases as the traffic load in the network increases, which adversely affects quality of the time-of-day synchronization under IEEE 1588.
One way to mitigate the effect of packet delay variation is to employ a hybrid system using synchronized Ethernet for synchronizing frequency and IEEE1588 for phase/time of the day synchronization. A drawback to this solution as currently implemented is that it is not possible to synchronize to the IEEE1588 source and the PRC at the same time, which means that while the time-of-day is being synchronized the frequency is tied to the local oscillator in the IEEE 1588 slave node. This oscillator has stability several orders of magnitude worse than the PRC.
Another major application of PLLs in telecom/datacom systems is to clean phase noise (jitter/wander) present at recovered clock at the output of PHY devices. Phase noise is divided into wander (phase noise frequencies less than 10 Hz) and jitter (phase noise frequencies above 10 Hz). A PLL behaves as a low pass filter for any phase noise present at its input reference. This property implies that phase noise can be reduced at the output of a PLL by reducing the loop bandwidth. However, while a PLL behaves as a low pass filter for any noise present at the input reference it also behaves as a high pass filter for any noise present at the local oscillator. In case of a digital PLL this is the noise coming from crystal oscillator (XO) or master clock that is used to drive the DCO. Although XOs are quite stable, their frequency is a function of temperature and some other factors (such as aging, voltage and vibration). Temperature is the most dominant factor. If an XO is used as the master clock for a digital PLL (DPLL), the loop bandwidth cannot be too low. With a narrow loop bandwidth the DPLL output will wander as the ambient temperature changes. As an example if the loop bandwidth is set at 0.1 Hz, than any jitter/wander with frequency above 0.1 Hz will appear at the DPLL output without any attenuation.
The problem of jitter/wander can partly be overcome by using Temperature Controlled Crystal Oscillators (TCXO) and Oven Controlled Crystal Oscillators (OCXOs) as the DPLL master clock. TCXOs have an electronic circuit that measures ambient temperature and, based on this measurement, adjusts the frequency of the XO to be as close as possible to nominal. OCXOs on the other hand have an oven that heats a crystal to a fixed temperature, which is higher than the ambient temperature specified for the OCXO. For example if the OCXO is specified to be used in the −40 C to 70 C range its oven temperature will typically be 85 C. An OCXO achieves stability by maintaining the temperature of the crystal at 85 C at all times regardless of the ambient temperature.
While they can achieve much better stability than simple XOs, TCXOs and OCXOs are much more expensive. Currently XOs are typically cost less than $1, TCXOs are in $15 to $50 range and OCXOs are generally over $50. However, these are not the only deficiencies of TCXOs and OCXOs. While TCXOs have higher long-term stability than XOs, they have larger high frequency jitter because an electronic circuit that constantly adjusts frequency of the crystal also injects noise. OCXOs on the other hand have comparable or better phase noise than regular XOs but they come in much bigger package, they burn much more power (to heat the oven) and have lower reliability (they run at high temperature all the time).
Another important reason for use of TCXOs and OCXOs as master clock is their long-term stability. When the DPLL loses all input references, the DPLL will go into holdover mode where the stability of its output frequency fully depends on the stability of the master clock oscillator (TCXO and OCXO).